Parameterized RC Extraction Using SPACE

The on-going reduction of the on-chip feature size goes together with an increase of process variability. While the manufacturer is expected to improve the uniformity of its output, and the designers are expected to enhance circuit adaptability and reliability, the design tools are expected to deliver convenient and fast approaches capable of giving accurate characterizations of manufacturing tolerances. In this paper, we will present an approach for parameterized RC extraction taking into account process variations. The proposed method is very efficient in the sense that it is an extension of standard extraction without considering variations, generating both the nominal values and the sensitivities within a very modest additional computational cost. The parameterized parasitic model can be easily applied in timing analysis and statistical analysis, for instance, statistical corner generation.